Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...

In an era when power has become a fundamental design constraint, questions persist about whether asynchronous logic has a role to play. It is a design style said to have significant benefits and yet ...

At 0.18 micron and below, handling crosstalk becomes a significant design challenge. Historically safe and pervasive design techniques may now increase crosstalk, and must be reviewed for suitability.

In the simulation and verification world, particularly with regard to system-on-a-chip (SoC) design closure, certain fault types have made their way to silicon with greater frequency. Many of today's ...

Today's SOC (system-on-chip) designs have dozens of clocks, many of which are asynchronous. This design approach facilitates the convergence of digital-audio, video, wireless, and networking ...

As the complexity of designs has scaled, the need for complete and accurate timing constraints (defined typically as Synopsys Design Constraints or SDC) has become extremely critical. High quality ...

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.